1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor devices and integrated circuits and, more particularly, to lithographic processes and tools for making lithographic resist exposure with an electron beam.
2. Description of the Prior Art
Lithographic processes are generally required in the manufacture of semiconductor integrated circuits. Even though there is a trend in the manufacture of integrated circuits to employ processes and element designs in which many processes are carried out in a self-aligned manner (both to avoid some lithographic processes and to produce structures at smaller size than can be accomplished lithographically), at least one lithographic process to define element locations is invariably required. A lithographic process, itself requires multiple steps of at least applying a resist, drying the resist, exposing the resist, developing the resist and then performing a material deposition or removal process, all of which are relatively time-consuming. Therefore, the lithographic processes are often a limiting factor in production line throughput.
Additionally, the small feature sizes of modern and foreseeable integrated circuits require extremely high-resolution exposures of the resist to be made. The lithographic technology almost exclusively in use in the industry at the present time is based on the use of light (radiation) as the exposure medium to expose the resist. Optical technology has advanced to the point that resolution is essentially limited by diffraction (or, more generally, interference effects of the radiation) but not significantly by imperfections of the optics known as aberrations. Diffraction is determined by the wavelength of the light used to expose the resist and is of generally lesser impact at shorter wavelengths.
Accordingly, the trend in the industry has been toward the use of shorter wavelengths of electromagnetic radiation to accommodate advances in integrated circuit manufacture allowing smaller dimensions and closer proximity of circuit elements. The current consensus in the industry is that the use of light is restricted to a wavelength of 193 nm (nanometers) which is in the deep ultra-violet (DUV) range and is believed to provide a maximum resolution supporting minimum pattern dimensions of between 130 and 180 nm.
Major efforts beyond this feature size limit are directed toward use of an extended range of electromagnetic radiation having wavelengths in the extreme ultra-violet (EUV) range and even X-rays. Use of charged particle (electron or ion) radiation, however, provides an alternative exposure medium for high resolution lithography. Use of either electrons or ions is not limited by diffraction effects but by other factors at the present state of the art. Such other factors include aberrations which are the equivalent of optical aberrations, often referred to as geometric aberrations, Coulomb interactions between the like-charged particles and interaction with the materials of the target toward which the particles are directed which results in scattering of the particles, causing an exposure effect known as proximity effect. While these effects are common to beams of either electrons or ions, electron beams are of primary interest in this context.
It is well-known that electron beams are readily controllable by magnetic and electric fields in the vicinity of the beam. Such control has been exploited for lithography in industry and research for about thirty years almost exclusively in configurations known as probe-forming systems. The term "probe" is used to indicate that the electron beam is formed in an electron optical column to produce a tiny spot at the target of the size of a few micrometers or less. This spot is then controlled in space and time by electric and/or magnetic fields to generate a desired pattern such as of a desired circuit pattern. However, to delineate a desired pattern over a chip of transverse dimensions in the range of several millimeters, the exposure is essentially a sequential process carried out over many thousands or millions of spots or "pixels" (although, as a practical matter, a spot can contain more than one pixel, for example, about 100 pixels in a shaped beam system; the term "pixel" being more generally equated with system resolution) and is therefore much more time-consuming than an exposure in an optical system in which an entire chip pattern can be exposed in a single flash. Aberrations can be controlled to some degree in probe-forming systems by applying corrections on a pixel-by-pixel basis as the sequential exposures of respective areas of the target are made.
In manufacture, the time required by a process and the throughput of apparatus with which the process is conducted is critical to the efficiency of the process. Consequently, electron beams have only been used for integrated circuit lithography in environments where the advantage of controllability by electric and magnetic fields is favorably balanced against their lack of high throughput. While direct exposure of chips on silicon wafers with electron beams has been in limited use for some years by a few manufacturers, e-beam systems are primarily employed in the fabrication of patterned optical masks for lithography systems employing projection of electromagnetic radiation.
To reduce the limitation on throughput of probe-forming systems, electron beam projection systems modeled on optical projection systems have been developed which shape the electron beam in accordance with a potentially complex mask referred to as a reticle, thus ideally projecting all pixels of the reticle in parallel. The use of demagnification allows very small feature sizes and fine pitches which may be smaller than feature sizes in the reticle and potentially smaller than may be available from spot exposures. However, some practical limitations of projection systems are encountered at even relatively small reticle sizes and relatively low throughputs. For example, correction of aberrations cannot be applied on a pixel-by-pixel basis as in probe-forming systems and the current state of the art does not support a lens which will cover a field corresponding to a reticle of 80.times.160 mm (corresponding to a 20.times.40 mm image at 4:1 linear demagnification) with sufficient fidelity to meet 0.25 micron or smaller feature size ground rules. Further, the electron emitting surface of the cathode electron source is imaged at the reticle and the physical size of the cathode required to produce sufficiently uniform illumination across the entire reticle is not available at the present time.
Accordingly, it has been proposed in U.S. Pat. No. 5,466,904, to Pfeiffer et al., assigned to the assignee of the present invention and fully incorporated by reference, to scan an electron beam across sub-sections of the reticle to reduce beam current requirements while allowing substantial aberration correction for respective sub-sections or sub-fields of the reticle and target plane. Substantial increase in throughput relative to probe-forming systems is supported since the respective exposures need not be made on a spot-by-spot basis (as the spot formed by the probe-forming system has been defined above) in serial step-and-repeat (S&R) fashion and the system is capable of exposing about 10.sup.7 pixels in parallel per sub-field while applying aberration corrections on a subfield-by-subfield basis.
Other fundamental functional elements in electron beam projection systems include the electron beam source structure such as that disclosed in U.S. Pat. No. 5,633,507, to Pfeiffer et al., and a lens arrangement by which the electron beam may be confined to a curvilinear axis which lies within a plane including the axis of the e-beam column (but is not constrained to do so) such as that disclosed in U.S. Pat. No. 5,635,719 to Petric (both of which are also assigned to the assignee of the present invention and fully incorporated by reference). U.S. Patent applications (Attorney Docket Nos. FI9-96-124, FI9-96-125, FI9-96-135 and FI9-97-033) also relate to curvilinear axis systems and are also fully incorporated by reference. The technique of the curvilinear axis disclosed in U.S. Pat. No. 5,635,719 to Petric may also be applied to a portion of the column serving to illuminate the reticle subfields in on-axis and off-axis locations to provide a wide scanning range without significant deterioration of the illumination uniformity.
Additionally, scattering of the electron beam in the reticle may be reduced in accordance with U.S. Pat. No. 5,674,413 to Pfeiffer et al., also assigned to the assignee of the present invention and incorporated by reference, thereby substantially increasing the beam current available for exposure and, accordingly, the throughput of the tool. Further, it is preferred to use as high an acceleration voltage as may be compatible with the beam imaging and positioning control electronics to reduce the resolution-limiting Coulomb interactions. A limit of about 180 kV is considered to be imposed by the possibility of damage to the reticle or wafer and structures previously formed thereon.
To reduce deflection requirements and accommodate both larger exposure fields on a wafer and the sequential processing of plural wafers, movement of the reticle and/or wafers is generally provided. Continuous circular motion of the reticle in combination with stepping motion of the wafer to reduce high movement speed of the reticle generally required in known reduction projection systems is disclosed in U.S. Pat. No. 5,434,424 to Stickel et al. A planar stage design to simplify the mechanical construction of the reticle or wafer stage to reduce weight and increase robustness as is required to meet high resolution requirements and accordingly minimize non-exposure time is disclosed in U.S. Pat. No. 5,140,242 to Doran et al. To reduce the vibrational interaction between the accelerating and decelerating reticle and wafer stages and the electron-optical column to improve system stability and exposure accuracy, a preferred frame design is disclosed in U.S. Pat. No. 5,508,518 to Kendall. All three of these patents are hereby fully incorporated by reference.
Combinations of some of these fundamental elements of an electron beam projection system deliver good results and high throughput for quarter micron or potentially much smaller feature size ground rules (e.g. 0.1 .mu.m) over a substantial range of operating conditions which may be chosen and adjusted at will by those skilled in the art to derive excellent lithographic results. However, while specific forms of these fundamental elements described in the U.S. Patents and Patent Applications incorporated by reference above are directed to improvement of resolution, reliability or speed of operation, it has not been demonstrated that these elements will fully cooperate to unconditionally provide high resolution and, simultaneously, high throughput, adequate for current and foreseeable integrated circuit designs and ground rules. On the contrary, unpredictable criticalities have been found to arise at smaller feature size ground rule regimes. Specifically, both the physical configuration and operating conditions of the e-beam projection system in relation to external factors such as resist sensitivity and internal factors, which include but are not limited to geometric aberrations, Coulomb interactions and electronic signal-to-noise ratio, impose significant trade-offs between e-beam column length and image reduction factor, beam current, beam accelerating voltage, beam scanning range, numerical aperture, subfield size, reticle and wafer stage velocity and accuracy and speed of control electronics for control of the beam and/or the reticle and/or target (e.g. wafer) transport mechanisms.
The combination of these trade-offs reflect a very complex system of interactions between the key parameters of physical configuration and operating conditions of each of the above fundamental elements (and potentially other elements) in combination which become extremely critical to provide performance in terms of throughput, feature resolution, linewidth and pattern overlay control required for lithography commensurate with manufacturing ground rules of 0.18 .mu.m critical dimension (CD) technology and smaller. In other words, to use a system including the technologies of the above-noted preferred fundamental elements to feature size ground rule regimes significantly smaller than a quarter-micron ground rule requires consideration and management of a system of interactions which is intractably large and complex and seemingly insusceptible of mathematical analysis. Development of empirical parameters in regard to physical configuration and operating conditions of each element and accounting for all interactions requires a significant number of experiments or simulations. No engineering analysis of the performance of an e-beam projection system comprehending all of the above-noted parameters and operating modes has been accomplished prior to the present invention.
For example, considering the fact that aberrations (such as those due to Coulomb interactions between like-charged electrons) and other positional errors will be present in some degree in all practical charged particle systems and that an acceptable aberration for a given feature size regime has to remain the same or an even smaller fraction of the feature size as the feature size is reduced, it may seem desirable to reduce aberrations by increasing the acceleration voltage of the electron beam which is known to reduce some aberrations. However, increasing the acceleration voltage effectively reduces resist sensitivity, for which increased beam current might be used to compensate to maintain throughput. Increased beam current increases Coulomb interactions between electrons and resultant aberrations, yielding only relatively slight gains while increasing the power dissipation requirements at beam-limiting diaphragms or apertures and of beam positioning and deflection devices, ultimately affecting beam stability and placement accuracy. Heating of the wafer or portions thereof causes uncontrollable changes in the resist chemistry and/or expansion and distortion of the wafer which may result in so-called overlay errors in the exposure pattern in quantitative dependence on beam placement, resist sensitivity and the like.
In the same manner, deflection errors tend to increase with the angular deflection of the electron beam and, to cover larger exposure fields (to the extent that larger exposure fields can be accommodated by lenses available within the level of present skill in the art), angular deflection can be reduced by increase of length of the e-beam column to maintain deflection displacements at smaller deflection angles. However, increase of the e-beam column length increases geometric aberrations as well as those due to Coulomb interactions. Compensation by scaling of the electron beam energy or accelerating voltage compromises throughput unless the beam current is further increased which may, in turn, compromise resolution and overlay accuracy, as discussed above. Again, the quantitative change in aberrations is also affected by magnification, lens configuration and the like in addition to the trade-off between field size and lens and corrector accuracy and the accuracy of positioning systems (which exhibit a limitation given by the speed-accuracy product of their design) for the reticle and wafer.
Thus, it can be appreciated that the physical configuration and operating parameters needed to apply the preferred, known, technologies discussed in the above-incorporated U.S. Patents and Patent Applications, in combination, to lithographic processes in smaller than quarter micron regimes is not at all straightforward, much less leading toward optimization, and the level of skill in the art does not assure success of any particular combination of structures of fundamental system elements at smaller feature size regimes consistent with maintaining an acceptable throughput of the system, much less a throughput comparable to optical exposure systems.
An approach to the complexity of this problem disclosed in U.S. Pat. No. 5,382,498 to Berger seeks to reduce the number of elements, conditions and interactions considered while extending electron beam projection lithography to smaller regimes and maintaining an acceptable level of throughput. Essentially, Berger is directed to a much larger feature size (half-micron) regime than discussed above and, beginning with the recognition that an effective limit of about 0.75 meters is imposed on e-beam column length at a relatively low beam current density of 10 mA/cm.sup.2 at the substrate due to Coulomb interactions, then rigorously optimizes the beam energy between effects of Coulomb interactions and thermal effects for a given resist sensitivity and reticle and wafer heat dissipation and coefficients of thermal expansion and elasticity. Adjustment of dwell time and the use of repeated scans is utilized in Berger to keep overlay error within acceptable limits but, understandably, may compromise throughput. Dwell time must also be coordinated with reticle and wafer movement to prevent image blurring at the wafer.
While Berger may be effective to produce acceptable results with acceptable throughput in half-micron feature size regimes, it does not provide a methodology to derive high throughput consistent with high resolution which is necessarily effective in the much smaller feature size regimes now required. Neither does Berger provide guidance toward suitable operating parameter ranges for fundamental elements of the lithography tool in combination or lead to any methodology for ensuring success of lithographic processes in such regimes, much less optimization thereof for maximized throughput and manufacturing yield at a required resolution in those regimes.